Course detail

Diagnosis and Safe Systems

FIT-DBSAcad. year: 2009/2010

Fault models of TTL, CMOS, PLA and bridge faults. Test generation methods. Structural tests. Functional tests. Sequential circuit testing. RTL level test generation. Random and pseudorandom test generation. Locating sequences. Fault dictionaries. Diagnostic data compression. Design for testability, structured methods. Built-in diagnosis. Memory testing. Processor and wiring testing. Fail-safe circuits. Instrumentation for diagnosis. Verification approaches.

Language of instruction

Czech

Number of ECTS credits

5

Mode of study

Not applicable.

Guarantor

doc. Ing. Vladimír Drábek, CSc.

Department

Department of Computer Systems (UPSY)

Learning outcomes of the course unit

Basic approaches to test generation and design for testability.

Prerequisites

There are no prerequisites

Co-requisites

Not applicable.

Planned learning activities and teaching methods

Not applicable.

Assesment methods and criteria linked to learning outcomes

Study evaluation is based on marks obtained for specified items. Minimimum number of marks to pass is 50.

Pass a mid-term exam, labs and a project.

Course curriculum

  • Poruchové modely obvodů TTL, CMOS, PLA, zkratů.
  • Test generation approaches.
  • Funkctional tests.
  • Sequential circuit testing.
  • Test generation at RTL level.
  • Random and pseudorandom test generation.
  • Location sequences.
  • Fault dictionaries.
  • Diagnostic data compression.
  • Design for testability.
  • Built-in diagnosis.
  • Memory testing.
  • Processor and wiring testing.
  • Fail-safe circuits.
  • Fault-tolerance priciples.
  • Diagnostic equipment.

Work placements

Not applicable.

Aims

To give the students the knowledge of methods for generation the tests for logic circuits, minimization and compression algorithms, and approaches to the design of testable circuits.

Specification of controlled education, way of implementation and compensation for absences

Mid-term exam, labs and a project.

Recommended optional programme components

Not applicable.

Prerequisites and corequisites

Not applicable.

Basic literature

Abramovici, M. - Breuer, M.A. - Friedman, A.D.: Digital Systems Testing and Testable Design, Computer Science Press, 1990 Drábek, V.: Vlastnosti a použití binárních celulárních automatů, habilitační práce, Brno 1997

Recommended reading

Přednáškové texty v elektronické podobě.

Classification of course in study plans

  • Programme IT-MSC-2 Master's

    branch MBI , 0 year of study, winter semester, elective
    branch MBS , 0 year of study, winter semester, elective
    branch MGM , 0 year of study, winter semester, elective
    branch MGM , 0 year of study, winter semester, elective
    branch MIN , 0 year of study, winter semester, elective
    branch MIN , 0 year of study, winter semester, elective
    branch MIS , 0 year of study, winter semester, elective
    branch MIS , 0 year of study, winter semester, elective
    branch MMI , 0 year of study, winter semester, elective
    branch MMM , 0 year of study, winter semester, elective
    branch MPS , 2 year of study, winter semester, elective
    branch MPV , 0 year of study, winter semester, elective
    branch MSK , 0 year of study, winter semester, elective

Type of course unit

 

Lecture

39 hod., optionally

Teacher / Lecturer

doc. Ing. Vladimír Drábek, CSc.

Syllabus

  • Poruchové modely obvodů TTL, CMOS, PLA, zkratů.
  • Test generation approaches.
  • Funkctional tests.
  • Sequential circuit testing.
  • Test generation at RTL level.
  • Random and pseudorandom test generation.
  • Location sequences.
  • Fault dictionaries.
  • Diagnostic data compression.
  • Design for testability.
  • Built-in diagnosis.
  • Memory testing.
  • Processor and wiring testing.
  • Fail-safe circuits.
  • Fault-tolerance priciples.
  • Diagnostic equipment.

Fundamentals seminar

10 hod., optionally

Teacher / Lecturer

doc. Ing. Vladimír Drábek, CSc.

Syllabus

  • Fault models for TTL, CMOS, PLA and bridge faults.
  • Test generation approaches.
  • Functional tests.
  • Sequential circuit testing.
  • RTL-level test generation.
  • Random and pseudorandom test generation.

Exercise in computer lab

8 hod., optionally

Teacher / Lecturer

doc. Ing. Vladimír Drábek, CSc.

Syllabus

  • Adder with built-in self test.
  • Linear feedback shift register.
  • Linear cellular automata.
  • Boundary scan testing.
  • Memory testing.

Project

8 hod., optionally

Teacher / Lecturer

doc. Ing. Vladimír Drábek, CSc.