Project detail

Verification and Validation Methods for Formal Descriptions

Duration: 01.01.1994 — 31.12.1996

On the project

1) Verification (software & hardware), testing, proof checking, temporal
logic, simulation, visualization, transformation, finite state machines.

2) Languages, formal semantics, standardization, specification, temporal
logic, process algebras, object orientation, data types, modularity,
non-functional aspects.

3) Implementation, tools

4) Case studies, distributed systems, intelligence networks

5) Real time

Keywords
verification, testing, proof checking, temporal logics, process algebras, tools, case studies

Mark

COST247

Default language

English

People responsible

Křetínský Mojmír, prof. RNDr., CSc. - fellow researcher
Šárek Milan - fellow researcher
Švéda Miroslav, prof. Ing., CSc. - fellow researcher

Units

Center of Information Services
- co-beneficiary (1994-01-01 - 1996-12-31)
Department of Information Systems
- co-beneficiary (2004-05-13 - not assigned)
Faculty of Informatics MU
- co-beneficiary (1994-01-01 - 1996-12-31)

Responsibility: