Performance Prediction Model of Bus-Based Shared Memory Architectures

article in a collection out of WoS and Scopus

English

It is shown that cache-coherent bus-based multiprocessor simulation can be implemented using message passing and few shared variables, at least in the case of an atomic bus and known coherence protocols. Data request and write-back bus transactions are generating messages to a shared memory server process, shared variables are used only for synchronization. A change in their values by one process is visible simultaneously to other processes, where it triggers invalidation/update actions. Models of various locks and barriers are described and the simulation-based performance prediction using Transim tool is illustrated on the example of parallel FFT benchmark in OpenMP. Multiprocessor hw, sw, and mapping to one another is described in Transim language that supports synchronous message passing as well as shared variables. Accuracy of prediction (8 %) has been satisfactory in the benchmark under test and may continue to be so in other benchmarks.

Bus-based multiprocessor, message passing model, performance prediction, multiprocessor simulation, OpenMP

DVOŘÁK, V.; STAROBA, J.

2002

22. 4. 2002

Ostrava

80-85988-71-2

Proceedings of 36th International Conference MOSIS'02 Modelling and Simulation of Systems

Vol. I.

273

280

8