An Abstraction of Multi-Port Memories with Arbitrary Addressable Units

article in a collection out of WoS and Scopus

English

The paper describes a technique for automatic generation of abstract models of memories that can be used for efficient formal verification of hardware designs. Our approach is able to handle addressing of different sizes of data, such as quad words, double words, words, or bytes, at the same time. The technique is also applicable for memories with multiple read and write ports, memories with read and write operations with zero- or single-clock delay, and it allows the memory to start with a random initial state allowing one to formally verify the given design for all initial contents of the memory. Our abstraction allows large register-files and memories to be represented in a way that dramatically reduces the state space to be explored during formal verification of microprocessor designs.

memory, register file, automatic formal verification, model checking

CHARVÁT, L.; SMRČKA, A.; VOJNAR, T.

2013

15. 2. 2013

The Universidad de Las Palmas de Gran Canaria

Las Palmas de Grand Canaria

978-84-695-6971-9

Proceedings of the 14th Computer Aided Systems Theory

254

255

2

https://www.fit.vut.cz/research/publication/10246/

eurocast13-abstract.pdf