NFA Reduction for Regular Expressions Matching Using FPGA

article in a collection out of WoS and Scopus

English

Many algorithms have been proposed to accelerate regular expression matching via mapping of a nondeterministic finite automaton into a circuit implemented in an FPGA. These algorithms exploit unique features of the FPGA to achieve high throughput. On the other hand the FPGA poses a limit on the number of regular expressions by its limited resources. In this paper, we investigate applicability of NFA reduction techniques - a formal aparatus to reduce the number of states and transitions in NFA prior to its mapping into FPGA. The paper presents several NFA reduction techniques, each with a different reduction power and time complexity. The evaluation utilizes regular expressions from Snort and L7 decoder. The best NFA reduction algorithms achieve more than 66% reduction in the number of states for a Snort ftp module. Such a reduction translates directly into 66% LUT and FF saving in the FPGA.

FPGA, NFA, Reduction, Regular expressions matching

KOŠAŘ, V.; ŽÁDNÍK, M.; KOŘENEK, J.

2013

9. 12. 2013

IEEE Computer Society

Kyoto

978-1-4799-2199-7

Proceedings of the 2013 International Conference on Field Programmable Technology

338

341

4

https://www.fit.vut.cz/research/publication/10306/

paper.pdf