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VAŠÍČEK, Z. SEKANINA, L.
Original Title
Evolutionary Design of Approximate Multipliers Under Different Error Metrics
Type
conference paper
Language
English
Original Abstract
Approximate circuits are digital circuits which are intentionally designed in such a way that the specification is not met in terms of functionality in order to obtain some improvements in power consumption, performance or area, in comparison with fully functional circuits. In this paper, we propose to design approximate circuits using evolutionary design techniques. In particular, different error metrics are utilized to assess the circuit functionality. The proposed method begins with a fully functional circuit which is then intentionally degraded by Cartesian genetic programming (CGP) to obtain a circuit with a predefined error. In the second phase, CGP is used to minimize the number of gates or another error criterion. The effect of various error metrics on the search performance, area and power consumption is evaluated in the task of multiplier design.
Keywords
approximate circuit, multiplier, evolutionary design
Authors
VAŠÍČEK, Z.; SEKANINA, L.
RIV year
2014
Released
16. 5. 2014
Publisher
IEEE Computer Society
Location
Warsaw
ISBN
978-1-4799-4558-0
Book
17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Pages from
135
Pages to
140
Pages count
6
URL
https://www.fit.vut.cz/research/publication/10513/
BibTex
@inproceedings{BUT111522, author="Zdeněk {Vašíček} and Lukáš {Sekanina}", title="Evolutionary Design of Approximate Multipliers Under Different Error Metrics", booktitle="17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems", year="2014", pages="135--140", publisher="IEEE Computer Society", address="Warsaw", doi="10.1109/DDECS.2014.6868777", isbn="978-1-4799-4558-0", url="https://www.fit.vut.cz/research/publication/10513/" }
Documents
ddecs14_noid.pdf