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DVOŘÁK, M. KOŘENEK, J.
Original Title
Low Latency Book Handling in FPGA for High Frequency Trading
Type
conference paper
Language
English
Original Abstract
Recent growth in algorithmic trading has caused a demand for lowering the latency of systems for electronic trading. FPGA cards are widely used to reduce latency and accelerate market data processing. To create a low latency trading system, it is crucial to effectively build a representation of the market state (book) in hardware. Thus, we have designed a new hardware architecture, which updates the book with the best bid/offer prices based on the incoming messages from the exchange. For each message a corresponding financial instrument needs to be looked up and its record needs to be updated. Proposed architecture is utilizing cuckoo hashing for the book handling, which enables low latency symbol lookup and high memory utilization. In this paper we discuss a trade-off between lookup latency and memory utilization. With average latency of 253 ns the proposed architecture is able to handle 119 275 instruments while using only 144 Mbit QDR SRAM.
Keywords
FPGA, Cuckoo hashing, HFT, High Frequency Trading,
Authors
DVOŘÁK, M.; KOŘENEK, J.
RIV year
2014
Released
23. 4. 2014
Publisher
IEEE Computer Society
Location
Warszawa
ISBN
978-1-4799-4558-0
Book
17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems
Pages from
175
Pages to
178
Pages count
4
URL
https://www.fit.vut.cz/research/publication/10622/
BibTex
@inproceedings{BUT111582, author="Milan {Dvořák} and Jan {Kořenek}", title="Low Latency Book Handling in FPGA for High Frequency Trading", booktitle="17th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems", year="2014", pages="175--178", publisher="IEEE Computer Society", address="Warszawa", doi="10.1109/DDECS.2014.6868785", isbn="978-1-4799-4558-0", url="https://www.fit.vut.cz/research/publication/10622/" }