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PODIVÍNSKÝ, J. ČEKAN, O. ZACHARIÁŠOVÁ, M. KOTÁSEK, Z.
Original Title
The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications
Type
conference paper
Language
English
Original Abstract
The aim of this paper is to present a new platform for estimating the fault-tolerance quality of electro-mechanical applications based on FPGAs. We demonstrate one working example of such EM application that was evaluated using our platform: the mechanical robot and its electronic controller in an FPGA. Different building blocks of the electronic robot controller allow to model different effects of faults on the whole mission of the robot (searching a path in a maze). In the experiments, the mechanical robot is simulated in the simulation environment, where the effects of faults injected into its controller can be seen. In this way, it is possible to differentiate between the fault that causes the failure of the system and the fault that only decreases the performance. Further extensions of the platform focus on the interconnection of the platform with the functional verification environment working directly in FPGA that allows automation and speed-up of checking the correctness of the system after the injection of faults.
Keywords
Fault Tolerance, Electro-mechanical Systems, Fault Injection, Single Event Upset, Functional verification
Authors
PODIVÍNSKÝ, J.; ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z.
RIV year
2014
Released
27. 8. 2014
Publisher
IEEE Computer Society
Location
Verona
ISBN
978-1-4799-5793-4
Book
17th Euromicro Conference on Digital Systems Design
Pages from
312
Pages to
319
Pages count
8
URL
https://www.fit.vut.cz/research/publication/10665/
BibTex
@inproceedings{BUT111616, author="Jakub {Podivínský} and Ondřej {Čekan} and Marcela {Zachariášová} and Zdeněk {Kotásek}", title="The Evaluation Platform for Testing Fault-Tolerance Methodologies in Electro-mechanical Applications", booktitle="17th Euromicro Conference on Digital Systems Design", year="2014", pages="312--319", publisher="IEEE Computer Society", address="Verona", doi="10.1109/DSD.2014.57", isbn="978-1-4799-5793-4", url="https://www.fit.vut.cz/research/publication/10665/" }