Publication detail

Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring

KEKELY, L. PUŠ, V. BENÁČEK, P. KOŘENEK, J.

Original Title

Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring

Type

conference paper

Language

English

Original Abstract

Current hardware acceleration cores for network traffic processing are often well optimized for one particular task and therefore provide high level of hardware acceleration. But for many applications, such as network traffic monitoring and security, it is also necessary to achieve rapid development cycle to provide fast response to security threats. We propose and evaluate a new concept of hardware acceleration for flexible flow-based network traffic monitoring with support of application protocol analysis. The concept is called Software Defined Monitoring (SDM) and it relies on a configurable hardware accelerator implemented in FPGA, coupled with smart monitoring tasks running as software on general CPU. The monitoring tasks in the software control the level of detail and type of information retained during the hardware processing. This arrangement allows rapid application prototyping in the software, followed by further shifting of the timing critical parts of the processing to the hardware accelerator. The concept is proposed with the scalability in mind, therefore it is suitable for different FPGA based platforms ranging from embedded single-chip solutions (such as Zynq or Cyclone V) to high-speed backbone network monitoring boxes. Our pilot high-speed implementation using FPGA acceleration board in a commodity server performs a 100 Gb/s flow traffic measurement augmented by a selected application protocol analysis.

Keywords

FPGA, Monitoring, Acceleration, Application protocols, L7

Authors

KEKELY, L.; PUŠ, V.; BENÁČEK, P.; KOŘENEK, J.

RIV year

2014

Released

2. 9. 2014

Publisher

IEEE Circuits and Systems Society

Location

Munich

ISBN

978-3-00-044645-0

Book

2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014)

Pages from

264

Pages to

267

Pages count

4

URL

BibTex

@inproceedings{BUT111645,
  author="Lukáš {Kekely} and Viktor {Puš} and Pavel {Benáček} and Jan {Kořenek}",
  title="Trade-offs and Progressive Adoption of FPGA Acceleration in Network Traffic Monitoring",
  booktitle="2014 24th International Conference on Field Programmable Logic and Applications (FPL 2014)",
  year="2014",
  pages="264--267",
  publisher="IEEE Circuits and Systems Society",
  address="Munich",
  doi="10.1109/FPL.2014.6927443",
  isbn="978-3-00-044645-0",
  url="https://www.fit.vut.cz/research/publication/10715/"
}