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PRISTACH, M. DVOŘÁK, V. FUJCIK, L.
Original Title
Enhanced Architecture of FIR Filters Using Block Memories
Type
conference paper
Language
English
Original Abstract
The paper presents an enhanced architecture of finite impulse response digital filters. The proposed architecture contains one multiply-accumulate unit and random access memory to store data. The architecture utilizes serial calculation to achieve minimum requirements on area. The architecture is suitable for implementation in application specific integrated circuits and field programmable gate arrays. The main advantages of the architecture are higher operating frequency, lower power consumption and smaller area utilization in particular cases.
Keywords
Digital signal processing; digital filter structures; finite impulse response; application specific integrated circuit; field-programmable gate array
Authors
PRISTACH, M.; DVOŘÁK, V.; FUJCIK, L.
RIV year
2015
Released
13. 5. 2015
Publisher
Institute of Electronics Silesian University of Technology
Location
Krakov, Polsko
ISBN
2405-8963
Periodical
IFAC-PapersOnLine (ELSEVIER)
Year of study
48
Number
4
State
Kingdom of the Netherlands
Pages from
306
Pages to
311
Pages count
6
BibTex
@inproceedings{BUT115938, author="Marián {Pristach} and Vojtěch {Dvořák} and Lukáš {Fujcik}", title="Enhanced Architecture of FIR Filters Using Block Memories", booktitle="13th IFAC Conference on Programmable Devices and Embedded Systems - PDeS 2015", year="2015", journal="IFAC-PapersOnLine (ELSEVIER)", volume="48", number="4", pages="306--311", publisher="Institute of Electronics Silesian University of Technology", address="Krakov, Polsko", doi="10.1016/j.ifacol.2015.07.052", issn="2405-8963" }