Publication detail

Memristor Model For Massively-Parallel Computations

BIOLEK, D. BIOLKOVÁ, V. KOLKA, Z.

Original Title

Memristor Model For Massively-Parallel Computations

Type

conference paper

Language

English

Original Abstract

The model of memristor described in the paper is designed for building models of large networks for analog computations. A circuit containing thousands of memristors for finding the shortest path in a complicated maze is a typical example. The model is designed to meet the following criteria: 1. It is a model of HP memristor with linear dopant drift while respecting the physical bounds of the internal state variable. 2. Reliable operation in the SPICE environment also when simulating extremely large networks. 3. Minimization of the simulation time while computing bias points and during transient analyses. A benchmark circuit for testing the applications of various complexities is presented. The results confirm a perfect operation of the model also in applications containing thousands of memristors.

Keywords

memristor; model; massively-parallel analog computations; SPICE

Authors

BIOLEK, D.; BIOLKOVÁ, V.; KOLKA, Z.

RIV year

2015

Released

4. 12. 2015

Publisher

IEEE

Location

Pointe aux Piments, Mauritius

ISBN

978-1-4673-9353-9

Book

2015 International Conference on Computing, Communication and Security (ICCCS)

Pages from

410

Pages to

414

Pages count

5

URL

http://ICCCS.in/

BibTex

@inproceedings{BUT119677,
  author="Dalibor {Biolek} and Viera {Biolková} and Zdeněk {Kolka}",
  title="Memristor Model For Massively-Parallel Computations",
  booktitle="2015 International Conference on Computing, Communication and Security (ICCCS)",
  year="2015",
  pages="410--414",
  publisher="IEEE",
  address="Pointe aux Piments, Mauritius",
  isbn="978-1-4673-9353-9",
  url="http://ICCCS.in/"
}