Publication detail

Instruction mapping process on the VLIW architectures

MEGO, R.

Original Title

Instruction mapping process on the VLIW architectures

Type

conference paper

Language

English

Original Abstract

This paper deals with the process of instruction mapping on the digital signal processors. This process is used by the newly developed tool, which is designed for generating low-level assembly code for very long instruction word processors. The tool is suitable for creating cores of the signal processing algorithms.

Keywords

instruction mapping; low-level; digital signal processing; very long instruction word

Authors

MEGO, R.

Released

28. 4. 2016

Publisher

Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií

Location

Brno

ISBN

978-80-214-5350-0

Book

Proceedings of the 22nd conference Student EEICT

Edition number

1

Pages from

385

Pages to

389

Pages count

5

BibTex

@inproceedings{BUT124268,
  author="Roman {Mego}",
  title="Instruction mapping process on the VLIW architectures",
  booktitle="Proceedings of the 22nd conference Student EEICT",
  year="2016",
  number="1",
  pages="385--389",
  publisher="Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií",
  address="Brno",
  isbn="978-80-214-5350-0"
}