Publication detail

Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays

SMÉKAL, D. FROLKA, J. HAJNÝ, J.

Original Title

Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays

Type

journal article in Web of Science

Language

English

Original Abstract

This article deals with encryption on Field Programmable Gate Array (FPGA). The first part describes current state of symmetric and asymmetric cryptography. The following part focuses on the AES algorithm and its implementation in VHDL language. The last part shows testing results of mentioned implementation on card NFB-40G2 containing FPGA from Xilinx series Virtex-7.

Keywords

AES, FPGA, VHDL, implementation, encryption, decryption, AddRoundKey, SubBytes, ShiftRows, MixColumns, NetCOPE

Authors

SMÉKAL, D.; FROLKA, J.; HAJNÝ, J.

Released

5. 10. 2016

Publisher

IFAC-PapersOnLine

ISBN

2405-8963

Periodical

IFAC-PapersOnLine (ELSEVIER)

Year of study

49

Number

25

State

Kingdom of the Netherlands

Pages from

384

Pages to

389

Pages count

6

URL

http://www.sciencedirect.com/science/article/pii/S2405896316327136

BibTex

@article{BUT127756,
  author="David {Smékal} and Jakub {Frolka} and Jan {Hajný}",
  title="Acceleration of AES Encryption Algorithm Using Field Programmable Gate Arrays",
  journal="IFAC-PapersOnLine (ELSEVIER)",
  year="2016",
  volume="49",
  number="25",
  pages="384--389",
  doi="10.1016/j.ifacol.2016.12.075",
  issn="2405-8963",
  url="http://www.sciencedirect.com/science/article/pii/S2405896316327136"
}