Publication detail

PRINCIPLE OF THE NEW ADJUSTED ARCHITECTURE OF R-2R D/A CONVERTER

POLEŠÁKOVÁ, Z.

Original Title

PRINCIPLE OF THE NEW ADJUSTED ARCHITECTURE OF R-2R D/A CONVERTER

Type

conference paper

Language

English

Original Abstract

This paper deals with a shortcoming that original R-2R D/A Converter architecture has – while resolution is bigger than 7 bits, switching of MSBs causes a significant non-linearity error, which may even cause DAC to be non-monotonous. A possible solution to this issue is shown in this paper: dividing MSBs into subbits of a lower weight. Analog circuitry and digital driving is published in this paper.

Keywords

Analog Integrated Circuits, D/A Conversion, DNL, INL, R-2R DAC, Small Chip Area

Authors

POLEŠÁKOVÁ, Z.

Released

21. 4. 2016

Publisher

Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií

Location

Brno

ISBN

978-80-214-5350-0

Book

STUDENT EEICT: Proceedings of the 22nd conference

Pages from

144

Pages to

146

Pages count

3

BibTex

@inproceedings{BUT127910,
  author="Zuzana {Bečková}",
  title="PRINCIPLE OF THE NEW ADJUSTED ARCHITECTURE OF R-2R D/A CONVERTER",
  booktitle="STUDENT EEICT: Proceedings of the 22nd conference",
  year="2016",
  pages="144--146",
  publisher="Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií",
  address="Brno",
  isbn="978-80-214-5350-0"
}