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MRÁZEK, V. VAŠÍČEK, Z.
Original Title
Automatic Design of Arbitrary-Size Approximate Sorting Networks with Error Guarantee
Type
conference paper
Language
English
Original Abstract
Despite the fact that hardware sorters offer great performance, they become expensive as the number of inputs increases. In order to address the problem of high-performance and power-efficient computing, we propose a scalable method for construction of power-efficient sorting networks suitable for hardware implementation. The proposed approach exploits the error resilience which is present in many real-world applications such as digital signal processing, biological computing and large-scale scientific computing. The method is based on recursive construction of large sorting networks using smaller instances of approximate sorting networks. The design process is tunable and enables to achieve desired tradeoffs between the accuracy and power consumption or implementation cost. A search-based design method is used to obtain approximate sorting networks. To measure and analyze the accuracy of approximate networks, three data-independent quality metrics are proposed. Namely, guarantee of error probability, worst-case error and error distribution are discussed. A significant improvement in the implementation cost and power consumption was obtained. For example, 20% reduction in power consumption was achieved by introducing a small error in 256-input sorter. The difference in rank is proved to be not worse than 2 with probability at least 99%. In addition to that, it is guaranteed that the worst-case difference is equal to 6.
Keywords
approximate computing sorting networks genetic programming
Authors
MRÁZEK, V.; VAŠÍČEK, Z.
Released
23. 9. 2016
Publisher
Institute of Electrical and Electronics Engineers
Location
Bremen
ISBN
978-1-5090-0733-2
Book
Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26rd International Workshop on
Pages from
221
Pages to
228
Pages count
8
URL
https://www.fit.vut.cz/research/publication/11175/
BibTex
@inproceedings{BUT133494, author="Vojtěch {Mrázek} and Zdeněk {Vašíček}", title="Automatic Design of Arbitrary-Size Approximate Sorting Networks with Error Guarantee", booktitle="Power and Timing Modeling, Optimization and Simulation (PATMOS), 2016 26rd International Workshop on", year="2016", pages="221--228", publisher="Institute of Electrical and Electronics Engineers", address="Bremen", doi="10.1109/PATMOS.2016.7833691", isbn="978-1-5090-0733-2", url="https://www.fit.vut.cz/research/publication/11175/" }