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SMÉKAL, D. HAJNÝ, J. MARTINÁSEK, Z.
Original Title
Packet Generators on Field Programmable Gate Array Platform
Type
conference paper
Language
English
Original Abstract
With the growing speed of computer networks, we need to test our solutions, network conditions, and topologies using high-speed traffic generators. The main contribution of this paper is 1) the theoretical proposal of a pseudo-random number generator (PRNG) algorithm that is usable for hardware-accelerated IP traffic generators and 2) the practical proposal of a novel design and implementation of an FPGA-based traffic generator that provides the high-speed generation of IP traffic for testing purposed, in particular for the Denial-of-Service (DoS) security testing. We present a solution for network cards based on FPGA and the NetCOPE development platform, in particular the NFB-40G2 cards. Using this platform, we explain the process of creating an IP packet and propose the VHDL architecture of the packet generator.
Keywords
Packet; Generator; FPGA; LFSR; pseudo-random number; NetCOPE
Authors
SMÉKAL, D.; HAJNÝ, J.; MARTINÁSEK, Z.
Released
5. 7. 2017
Location
Barcelona, Španělsko
ISBN
978-1-5090-3982-1
Book
2017 40th International Conference on Telecommunications and Signal Processing (TSP)
1805-5435
Periodical
International Conference on Telecommunications and Signal Processing (TSP)
State
Czech Republic
Pages from
97
Pages to
100
Pages count
4
URL
http://ieeexplore.ieee.org/abstract/document/8075944/
BibTex
@inproceedings{BUT135463, author="David {Smékal} and Jan {Hajný} and Zdeněk {Martinásek}", title="Packet Generators on Field Programmable Gate Array Platform", booktitle="2017 40th International Conference on Telecommunications and Signal Processing (TSP)", year="2017", journal="International Conference on Telecommunications and Signal Processing (TSP)", pages="97--100", address="Barcelona, Španělsko", doi="10.1109/TSP.2017.8075944", isbn="978-1-5090-3982-1", issn="1805-5435", url="http://ieeexplore.ieee.org/abstract/document/8075944/" }