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PETRŽELA, J.
Original Title
New network structures of reconfigurable fractional-order PID regulators with DVCC
Type
conference paper
Language
English
Original Abstract
This brief paper shows design procedure towards new non-integer order proportion al-integrative-derivative (PID) regulators with single grounded two-terminal device known as constant phase element (CPE). Proposed concept is based on the modified matrix method of unknown nodal voltages originally invented to analyze linearized lumped circuits. New topologies of PID regulators are obtained by handling with pseudo-admittance matrix prefilled by fixed connection of single differential voltage current conveyor (DVCC). Unique property of designed circuits is orthogonal electronical reconfiguration of the voltage transfer function by using external control quantities; this is achieved thanks to a suitable interconnection of several operational trans- admittance amplifiers (OTA). It is shown by using frequency- and time-domain Orcad Pspice circuit simulations that network topologies provided in this manuscript allows smooth closed-loop feedback control dynamics. Limited validity of a passive ladder approximation of CPE together with the parasitic properties of DVCC as well as OTA causes limitations of regulator function; these aspects are theoretically analyzed. Finally, further practical perspectives in area of PID regulation are shortly discussed.
Keywords
differential difference voltage current conveyor; feedback control; lumped circuit synthesis; PID regulator; unknown nodal voltages
Authors
Released
22. 6. 2017
Location
Bydgoszcz (Poland)
ISBN
978-83-63578-11-4
Book
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems
Pages from
527
Pages to
531
Pages count
5
URL
https://ieeexplore.ieee.org/document/8005268
BibTex
@inproceedings{BUT137873, author="Jiří {Petržela}", title="New network structures of reconfigurable fractional-order PID regulators with DVCC", booktitle="Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems", year="2017", pages="527--531", address="Bydgoszcz (Poland)", doi="10.23919/MIXDES.2017.8005268", isbn="978-83-63578-11-4", url="https://ieeexplore.ieee.org/document/8005268" }