Publication detail

Towards Evolvable IP Cores for FPGAs

SEKANINA, L.

Original Title

Towards Evolvable IP Cores for FPGAs

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

The paper deals with a new approach to the design of adaptive hardware using common Field Programmable Gate Arrays (FPGA). The ultimate aim is to develop evolvable IP (Intellectual Property) cores. The cores should be reused in the same way as ordinary IP cores are reused. In contrast to the conventional cores, the evolvable cores are able to perform autonomous evolution of their internal circuits. The cores should be available in the form of HDL source code, i.e. they should be synthesizable into any reconfigurable device of a sufficient capacity. The approach is based on implementation of a virtual reconfigurable circuit and a genetic unit in an ordinary FPGA. In the presented case study an adaptive image filter is designed, implemented and synthesized. The proposed idea of evolvable IP core could open the way towards defining a business model for evolvable hardware.

Keywords

evolvable hardware, IP core, digital circuit

Authors

SEKANINA, L.

RIV year

2003

Released

7. 5. 2003

Publisher

IEEE Computer Society Press

Location

Los Alamitos

ISBN

0-7695-1977-6

Book

Proc. of The 2003 NASA/DoD Conference on Evolvable Hardware

Pages from

145

Pages to

154

Pages count

10

URL

https://www.fit.vut.cz/research/publication/7185/

BibTex

@inproceedings{BUT13979,
  author="Lukáš {Sekanina}",
  title="Towards Evolvable IP Cores for FPGAs",
  booktitle="Proc. of The 2003 NASA/DoD Conference on Evolvable Hardware",
  year="2003",
  pages="145--154",
  publisher="IEEE Computer Society Press",
  address="Los Alamitos",
  isbn="0-7695-1977-6",
  url="https://www.fit.vut.cz/research/publication/7185/"
}