Publication detail

Testable Design Verification Using Petri Nets

RŮŽIČKA, R.

Original Title

Testable Design Verification Using Petri Nets

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In the paper, a method for formal verification of testable design is presented. As a input, a digital circuit structure at RT level designed using any DfT technique is assumed. Proposed method enables to verify testability of each element or a part of the circuit. Petri Net based model and common methods of Petri Net analysis are utilised. On the model, it is possible to prove, if a circuit element or a part of the circuit under test can be tested by a selected way - if paths, chosen for diagnostic data transport, are passable or not and if not, for what reason.

Keywords

Testability Analysis, Testability Verification, Petri Nets, I path, RTL Digital Circuits

Authors

RŮŽIČKA, R.

RIV year

2003

Released

1. 9. 2003

Publisher

IEEE Computer Society Press

Location

Los Alamitos, CA

ISBN

0-7695-2003-0

Book

Proceedings of Euromicro Symposium on Digital System Design 2003

Pages from

304

Pages to

311

Pages count

8

BibTex

@inproceedings{BUT14194,
  author="Richard {Růžička}",
  title="Testable Design Verification Using Petri Nets",
  booktitle="Proceedings of Euromicro Symposium on Digital System Design 2003",
  year="2003",
  pages="304--311",
  publisher="IEEE Computer Society Press",
  address="Los Alamitos, CA",
  isbn="0-7695-2003-0"
}