Publication detail

A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation

LOJDA, J. KOTÁSEK, Z.

Original Title

A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

In this presentation, an approach to fault-tolerant systems design and synthesis based on High-level Synthesis (HLS) is shown. A description and evaluation of the impacts of HLS optimization methods are shown as well. The higher reliability is achieved through modification of input description in the C++ programming language, which the HLS synthesis tools are based on. Our work targets SRAM-based FPGAs, which are prone to Single Event Upsets (SEUs). For the evaluation of the impacts of faults we use our evaluation platform, which allows us to test fault tolerance properties of the Design Under Test (DUT). The evaluation platform is based on functional verification combined with fault injection.

Keywords

High-level Synthesis, Data-Path, CatapultC, Fault Tolerance, Fault-Tolerant, Robot Controller, C++

Authors

LOJDA, J.; KOTÁSEK, Z.

Released

29. 6. 2017

Publisher

Faculty of Information Technology, Czech Technical University

Location

Roztoky u Prahy

ISBN

978-80-01-06178-7

Book

Proceedings of the 5th Prague Embedded Systems Workshop

Pages from

79

Pages to

80

Pages count

2

URL

https://www.fit.vut.cz/research/publication/11451/

BibTex

@inproceedings{BUT144442,
  author="Jakub {Lojda} and Zdeněk {Kotásek}",
  title="A Basic Approach to Fault Tolerance of Data Paths of HLS-synthesized Systems and its Evaluation",
  booktitle="Proceedings of the 5th Prague Embedded Systems Workshop",
  year="2017",
  pages="79--80",
  publisher="Faculty of Information Technology, Czech Technical University",
  address="Roztoky u Prahy",
  isbn="978-80-01-06178-7",
  url="https://www.fit.vut.cz/research/publication/11451/"
}

Documents

PESW_2017_lojda.pdf