Publication detail

Mapping of P4 Match Action Tables to FPGA

KEKELY, M. KOŘENEK, J.

Original Title

Mapping of P4 Match Action Tables to FPGA

Type

conference paper

Language

English

Original Abstract

Current networks are changing very fast. Network administrators needmore flexible and powerful tools to be able to support new protocols or services very fast. The P4 language provides new level of abstraction for flexible packet processing. Therefore, we have designed new architecture for memory efficient mapping of P4 match/action tables to FPGA. The architecture is based on DCFL algorithm and is able to balance the processing speed and available memory resources.

Keywords

P4, FPGA, packet classification, match action tables

Authors

KEKELY, M.; KOŘENEK, J.

Released

4. 9. 2017

Publisher

Institute of Electrical and Electronics Engineers

Location

Ghent

ISBN

978-90-90-30428-1

Book

Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS

Pages from

1

Pages to

2

Pages count

2

BibTex

@inproceedings{BUT144482,
  author="Michal {Kekely} and Jan {Kořenek}",
  title="Mapping of P4 Match Action Tables to FPGA",
  booktitle="Preceedings of 27TH INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE LOGIC AND APPLICATIONS",
  year="2017",
  pages="1--2",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Ghent",
  doi="10.23919/FPL.2017.8056768",
  isbn="978-90-90-30428-1"
}