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KHATEB, F. KULEJ, T.
Original Title
Design and Implementation of a 0.3-V Differential Difference Amplifier
Type
journal article in Web of Science
Language
English
Original Abstract
A new silicon realization of an ultra low voltage (LV) and ultra low power (LP) differential-difference amplifier (DDA) is presented in this paper. The circuit combines the idea of non-tailed bulk-driven (BD) differential pairs with a partial positive feedback used for voltage gain boosting. The DDA operates from VDD ranging from 0.3 to 0.5 V. For a 0.3-V version the circuit provides measured DC voltage gain larger than 60 dB, the GBW product of 1.85 kHz, PSRR of 57 dB and the average slew-rate (SR) of 1.55 V/ms at 20 pF load capacitance, while consuming only 22nW of power. An instrumentation amplifier (IA) based on the proposed DDA showed the THD of 0.5 % for Vin=50mVpp, and the 3-dB bandwidth of 750 Hz with the voltage gain of 2 V/V. The circuit has been fabricated in a standard n-well 0.18 um CMOS process from TSMC. Chip test results agree well with simulations. A special design procedure has also been developed that allows the circuit to be optimized under such extreme supply conditions.
Keywords
Bulk-driven, differential difference amplifier, Low-voltage CMOS, Low-power CMOS
Authors
KHATEB, F.; KULEJ, T.
Released
15. 3. 2019
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Location
USA
ISBN
1549-8328
Periodical
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS
Year of study
66
Number
2, IF: 3.934
State
United States of America
Pages from
513
Pages to
523
Pages count
11
URL
https://doi.org/10.1109/TCSI.2018.2866179
BibTex
@article{BUT148750, author="Fabian {Khateb} and Tomasz {Kulej}", title="Design and Implementation of a 0.3-V Differential Difference Amplifier", journal="IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS", year="2019", volume="66", number="2, IF: 3.934", pages="513--523", doi="10.1109/TCSI.2018.2866179", issn="1549-8328", url="https://doi.org/10.1109/TCSI.2018.2866179" }