Publication detail

Automation of Processor Verification Using Recurrent Neural Networks

FAJČÍK, M. SMRŽ, P. ZACHARIÁŠOVÁ, M.

Original Title

Automation of Processor Verification Using Recurrent Neural Networks

Type

conference paper

Language

English

Original Abstract

When  considering  simulation-based  verification  of processors, the current trend is to generate stimuli using pseudo-random  generators  (PRGs),  apply  them  to  the  processor  inputs and monitor the achieved coverage of its functionality in order to determine  verification  completeness.  Stimuli  can  have  different forms, for example, they can be represented by bit vectors applied to  the  input  ports  of  the  processor  or  by  programs  that  are loaded  directly  into  the  program  memory.  In  this  paper,  we propose  a  new  technique  dynamically  altering  constraints  for PRG  via  recurrent  neural  network,  which  receives  a  coverage feedback from the simulation of design under verification. For the demonstration purposes we used processors provided by Codasip as  their  coverage  state  space  is  reasonably  big  and  differs  for various  kinds  of  processors.  Nevertheless,  techniques  presented in  this  paper  are  widely  applicable.  The  results  of  experiments show that not only the coverage closure is achieved much sooner, but we are able to isolate a small set of stimuli with high coverage that  can  be  used  for  running  regression  tests.

Keywords

Functional Verification, Automation of Verification, Neural network, Recurrent Neural Network, Hopfield Net-work,  UVM,  Coverage-Driven  Verification,  Optimization  Problem,  Combinatorial  Optimization

Authors

FAJČÍK, M.; SMRŽ, P.; ZACHARIÁŠOVÁ, M.

Released

27. 12. 2017

Publisher

Institute of Electrical and Electronics Engineers

Location

Austin, Texas

ISBN

978-1-5386-3351-9

Book

18th International Workshop on Microprocessor and SOC Test, Security and Verification (MTV)

Pages from

15

Pages to

20

Pages count

6

URL

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8396943

BibTex

@inproceedings{BUT154991,
  author="Martin {Fajčík} and Pavel {Smrž} and Marcela {Zachariášová}",
  title="Automation of Processor Verification Using Recurrent Neural Networks",
  booktitle="18th International Workshop on Microprocessor and SOC Test, Security and   Verification (MTV)",
  year="2017",
  pages="15--20",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Austin, Texas",
  doi="10.1109/MTV.2017.15",
  isbn="978-1-5386-3351-9",
  url="https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8396943"
}