Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis

conference paper

English

During the last decades, electronic systems became an important matter of controlling many critical processes. However, those critical processes often require increased reliability. This requirement puts pressure on system developers to make systems reliable. Because of ever growing chip-level integration, capabilities of electronic systems are expanding, and, thus, leading to more complex system architectures, significantly increasing the number of man-hours needed to develop such systems. Many people believe the solution is to move the development to a higher level of abstraction (e.g. an algorithm level) and use the so-called High-Level Synthesis (HLS) for this purpose. In this research, we aimed towards a decision, whether the usage of HLS impacts the resulting reliability properties of the system, and, thus, whether the HLS-generated system matches reliability properties of its corresponding VHDL-implemented version. We found out that, for the selected set of circuits, HLS performs better in terms of resource consumption, but, also, which we consider surprising, in terms of reliability. For the selected set, HLS achieved better reliability by 3.03 percentage points in contrast to the classical approach utilizing a traditional Hardware Description Language (HDL). In these experiments, no redundancy was intentionally inserted into benchmarking circuits.

High-Level Synthesis, Fault Tolerance Evaluation, Fault Tolerance Estimation Framework, Catapult C, C++, VHDL.

LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.

14. 9. 2018

IEEE Computer Society

Kazan

978-1-5386-5710-2

Proceedings of IEEE East-West Design & Test Symposium

80

86

7

https://www.fit.vut.cz/research/publication/11752/