Scalable Construction of Approximate Multipliers With Formally Guaranteed Worst Case Error

journal article in Web of Science

English

Approximate computing exploits the fact that many applications are inherently error resilient. In order to reduce power consumption, approximate circuits such as multipliers have been employed in these applications. However, most current approximate multipliers are based on ad-hoc circuit structures and, for automated circuit approximation methods, large efficient designs are difficult to find due to the increased search space. Moreover, existing design methods do not typically provide sufficient formal guarantees in terms of error if large approximate multipliers are constructed. To address these challenges, this brief introduces a general and efficient method for constructing large high-quality approximate multipliers with respect to the objectives formulated in terms of the power-delay product and a provable error bound. This is demonstrated by means of a comparative evaluation of approximate 16-bit multipliers constructed by the proposed method and other methods in the literature.

Approximate computing circuits and systems, circuit synthesis, circuits, computers and information processing

MRÁZEK, V.; VAŠÍČEK, Z.; SEKANINA, L.; JIANG, H.; HAN, J.

1. 11. 2018

1063-8210

IEEE Trans. on VLSI Systems.

26

11

United States of America

2572

2576

5

https://www.fit.vut.cz/research/publication/11678/

08423431.pdf