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LOJDA, J. PODIVÍNSKÝ, J. ČEKAN, O. PÁNEK, R. KOTÁSEK, Z.
Original Title
FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation
Type
conference paper
Language
English
Original Abstract
The complexity of today's systems is growing along with the level of chip integration. This results in higher demand for reliability techniques; it also increases the difficulty of incorporating reliability in such systems. For this purpose, we are working on a method to automate reliability insertion; however, for this method, it is necessary to have feedback on the result. In this paper, one component of the automation flow enabling the estimation of the resulting reliability - Fault Tolerance ESTimation (FT-EST) framework - is presented along with an improvement for accelerating the time necessary to reach the estimation. For the purpose of evaluation, we are using our Redundant Data Types approach, which enables us to intentionally insert reliability in a particular operation. The estimation utilizes the concept of fault injection. The results indicate, that the concept of Redundant Data Types is functional, however, also suggest its future improvements (e.g. for the operation of subtraction).
Keywords
Fault-Tolerant, Fault Tolerance Property Estimation, FT-EST, Verification, High-Level Synthesis, Redundant Data Type.
Authors
LOJDA, J.; PODIVÍNSKÝ, J.; ČEKAN, O.; PÁNEK, R.; KOTÁSEK, Z.
Released
29. 8. 2018
Publisher
IEEE Computer Society
Location
Praha
ISBN
978-1-5386-7376-8
Book
Proceedings of the 2018 21st Euromicro Conference on Digital System Design
Pages from
244
Pages to
251
Pages count
8
URL
https://www.fit.vut.cz/research/publication/11707/
BibTex
@inproceedings{BUT155032, author="Jakub {Lojda} and Jakub {Podivínský} and Ondřej {Čekan} and Richard {Pánek} and Zdeněk {Kotásek}", title="FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant Systems Design Automation", booktitle="Proceedings of the 2018 21st Euromicro Conference on Digital System Design", year="2018", pages="244--251", publisher="IEEE Computer Society", address="Praha", doi="10.1109/DSD.2018.00053", isbn="978-1-5386-7376-8", url="https://www.fit.vut.cz/research/publication/11707/" }
Documents
DSD18_Lojda_et_al.pdf