Publication detail

Optimum Polymorphic Circuits Synthesis Method

FIŠER, P. ŠIMEK, V.

Original Title

Optimum Polymorphic Circuits Synthesis Method

Type

conference paper

Language

English

Original Abstract

Polymorphic circuits represent a newly emerging computation paradigm, where one hardware structure is capable to  perform two or more different intended functions, depending on instantaneous conditions in the target operating environment. Due to the peculiarity of this paradigm, design of these circuits also calls for a novel approach to logic synthesis procedures. Several attempts to enhance the design of such circuits have already been made, producing highly suboptimal solutions. As an ingenious attempt to set lower bounds on complexity and support designers of sophisticated logic synthesis algorithms, a method with the prospect to facilitate the generation of optimum-size polymorphic circuits is presented in this  paper. The core of the proposed method is based on a purposeful exploitation of formal techniques, comprising SAT and PBO in the first place.

Keywords

Polymorphic circuits, Boolean functions, logic synthesis, SAT.

Authors

FIŠER, P.; ŠIMEK, V.

Released

22. 5. 2018

Publisher

IEEE Circuits and Systems Society

Location

Taormina

ISBN

978-1-5386-5290-9

Book

13th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)

Pages from

1

Pages to

6

Pages count

6

URL

https://www.fit.vut.cz/research/publication/11740/

BibTex

@inproceedings{BUT155056,
  author="Petr {Fišer} and Václav {Šimek}",
  title="Optimum Polymorphic Circuits Synthesis Method",
  booktitle="13th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS)",
  year="2018",
  pages="1--6",
  publisher="IEEE Circuits and Systems Society",
  address="Taormina",
  doi="10.1109/DTIS.2018.8368585",
  isbn="978-1-5386-5290-9",
  url="https://www.fit.vut.cz/research/publication/11740/"
}

Documents

14-1.pdf