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LOJDA, J. KOTÁSEK, Z.
Original Title
Fault Tolerance in HLS for the Purposes of Reliable System Design Automation
Type
article in a collection out of WoS and Scopus
Language
English
Original Abstract
In the presentation, existing method to insert redundancy into HLS-generated systems will be briefly described alongside with its improvement in the form of a majority function selection. We found out that the type of the majority function affects not only the resulting reliability, but also the resources consumption. The presentation also addresses the level of redundancy selection, as we evaluated various numbers of redundant modules with multiple fault occurrences. The case study experiments are carried out with our robot verification platform utilizing the so-called left-hand algorithm and fault injection into a Field Programmable Gate Array (FPGA) implementing the robot controller. This approach is not limited to FPGAs, however, we use an FPGA technology during the evaluation for its wide range of applications and its versatility.
Keywords
Fault Tolerance, High-Level Synthesis, Catapult C, Electronic Design Automation, Robot Controller, C++
Authors
LOJDA, J.; KOTÁSEK, Z.
Released
28. 6. 2018
Publisher
Faculty of Information Technology, Czech Technical University
Location
Roztoky u Prahy
ISBN
978-80-01-06456-6
Book
Proceedings of the 6th Prague Embedded Systems Workshop
Pages from
31
Pages to
32
Pages count
2
URL
https://www.fit.vut.cz/research/publication/11743/
BibTex
@inproceedings{BUT155058, author="Jakub {Lojda} and Zdeněk {Kotásek}", title="Fault Tolerance in HLS for the Purposes of Reliable System Design Automation", booktitle="Proceedings of the 6th Prague Embedded Systems Workshop", year="2018", pages="31--32", publisher="Faculty of Information Technology, Czech Technical University", address="Roztoky u Prahy", isbn="978-80-01-06456-6", url="https://www.fit.vut.cz/research/publication/11743/" }