Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation

conference paper

English

Field Programmable Gate Arrays (FPGAs) are popular not only for their wide range of usage in embedded systems, however, they are susceptible to radiation effects. Charged particles cause the so-called Single Event Upsets (SEUs) in their configuration memory. SEUs can induce failure of the whole system. This problem is fundamental for space applications where sun radiation is more considerable than in the Earth. Two main approaches to SEU mitigation technique exist: fault masking and reparation. The most popular masking method is Triple Modular Redundancy (TMR). For the faults reparation, FPGA's capability of reconfiguration is used. It is possible to combine these approaches to obtain improved fault tolerant system. It is important to assess reliability rate of this system and, therefore, its estimation by a simulation is the main part of this paper. We propose evaluation environment which assesses the reliability of a TMR system with malfunction module reconfiguration depending on faults occurrence frequency and reconfiguration time necessary for fault reparation.

Fault Tolerant System, FPGA, Partial Reconfiguration, Simulation.

PÁNEK, R.; LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.

14. 9. 2018

IEEE Computer Society

Kazaň

978-1-5386-5710-2

Proceedings of IEEE East-West Design & Test Symposium

129

134

6

https://www.fit.vut.cz/research/publication/11758/

EWDTS18_Panek_et_al.pdf