Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems

conference paper

English

As electronic systems penetrate into areas in which reliable computing is required, new methods incorporating reliability into these systems arise. It is important to properly test and evaluate parameters of such methods before the actual implementation and the practical usage in an application. Generally, in our research, we are focusing on the acceleration of reliable design through creation of automation methods. However, for this purpose, it is important to develop tools to automatically analyze reliability properties of the system after the method is applied. In our previous work, we developed the Fault Tolerance ESTimation (FT-EST) framework, which specializes on minimizing the requirement for user intervention. In this paper, we are using the framework to collect the data, however, the research presented in this paper primarily focuses on the possibility to automatically analyze such data. Our previous papers were focused on particular methods of the automatic reliability insertion and evaluation while this paper introduces new reliability indicators based on low-level properties of FPGA configuration bitstreams. Currently, we are limiting our research to SRAM-based FPGA systems and focus on the VHDL and C++ (in the combination with High-level Synthesis) languages.

Fault Tolerance Evaluation, Fault-tolerant Design Automation, Analysis, FPGA, Fault Tolerance Estimation Tool, High-level Synthesis, Catapult C, Redundant Data Type

LOJDA, J.; PODIVÍNSKÝ, J.; KOTÁSEK, Z.

11. 3. 2019

IEEE Computer Society

Santiago

978-1-7281-1756-0

20th IEEE Latin American Test Symposium (LATS 2019)

93

96

4

https://www.fit.vut.cz/research/publication/11870/

LATS19_Lojda_et_al.pdf