Publication detail

Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures

ŠŤÁVA, M.

Original Title

Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures

Type

conference paper

Language

English

Original Abstract

This paper presents a novel online fault tolerance method for network-on-chip (NoC) interconnects targeting both permanent and transient faults. We introduce a concept of retransmission credit as a method of distinguishing between permanent and transient faults. Another concept of monitoring errors separately on two types of interconnects – inter-switch links and intra-switch input/output port paths – is also employed. The concept introduced allows more efficient routing in comparison to existing error recovery schemes. Experimental validation shows that the proposed NoC error recovery scheme utilising both the concepts delivers better or at least similar performance when compared to existing NoC error recovery schemes.

Keywords

fault tolerance, error recovery, network on chip, permanent or transient fault, performance

Authors

ŠŤÁVA, M.

Released

30. 5. 2019

Publisher

IEEE

ISBN

978-1-7281-0073-9

Book

22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019

ISBN

2473-2117

Periodical

IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems

State

United States of America

Pages from

1

Pages to

4

Pages count

4

BibTex

@inproceedings{BUT156411,
  author="Martin {Šťáva}",
  title="Efficient Error Recovery Scheme in Fault-tolerant NoC Architectures",
  booktitle="22nd International Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2019",
  year="2019",
  journal="IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems",
  pages="1--4",
  publisher="IEEE",
  doi="10.1109/DDECS.2019.8724641",
  isbn="978-1-7281-0073-9",
  issn="2473-2117"
}