Publication detail

A Novel Background Calibration in 10-bit, 40 MHz, 54 mW Pipelined ADC Using Switched-capacitor Approach

HÁZE, J. VRBA, R.

Original Title

A Novel Background Calibration in 10-bit, 40 MHz, 54 mW Pipelined ADC Using Switched-capacitor Approach

Type

conference paper

Language

English

Original Abstract

The article describes a new background calibration technique, which is used in new 10-bit low power pipelined ADC. The switched-capacitor approach (SC) is utilized in proposed ADC as well. The low power consumption is one of the most important issues considered in the design, because the ADC is intended for using in portable applications. Well-known operational-amplifier (op-amp) sharing technique was modified and used to decrease the power usage. The capacitor scaling approach is suitable for the same purpose. The basic problems coupled to SC such as clock feedthrough from digital part through the switches, capacitor mismatch and op-amp non-idealities have been taken into account in design of the ADC. These error sources are canceled or roughly attenuated by means of novel background calibration or using known analog-domain techniques. The special op-amps and comparators were designed for this purpose. The power consumption of the op-amps was taken into account too.

Keywords

Pipelined ADC, switched-capacitors, background calibration, portable devices

Authors

HÁZE, J.; VRBA, R.

RIV year

2005

Released

1. 1. 2005

Publisher

UREL Brno

Location

Brno

ISBN

80-214-3089-3

Book

Seminář o řešení projektu GA ČR 102/03/H105, Moderní metody řešení, návrhu

Pages from

47

Pages to

55

Pages count

9

BibTex

@inproceedings{BUT15679,
  author="Jiří {Háze} and Radimír {Vrba}",
  title="A Novel Background Calibration in 10-bit, 40 MHz, 54 mW Pipelined ADC Using Switched-capacitor Approach",
  booktitle="Seminář o řešení projektu GA ČR 102/03/H105, Moderní metody řešení, návrhu",
  year="2005",
  pages="9",
  publisher="UREL Brno",
  address="Brno",
  isbn="80-214-3089-3"
}