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KEKELY, L. CABAL, J. KOŘENEK, J.
Original Title
Effective FPGA Architecture for General CRC
Type
conference paper
Language
English
Original Abstract
As throughputs of digital networks and memory interfaces are on a constant rise, there is a need for ever-faster implementations of error-detecting codes. Cyclic redundancy checks (CRC) are a common and widely used type of codes to ensure consistency or detect accidental changes of transferred data. We propose a novel FPGA architecture for the computation of the CRC values designed for general high-speed data transfers. Its key feature is allowing a processing of multiple independent data packets (transactions) in each clock cycle, what is a necessity for achieving high overall throughput on very wide data buses. The proposed approach can be effectively used in Ethernet MACs for different speeds, in Hybrid Memory Cube (HMC) controller, and in many other technologies utilizing any kind of CRC. Experimental results confirm that the proposed architecture enables reaching an effective throughput sufficient for utilization in multi-terabit Ethernet networks (over 2 Tbps or over 3000 Mpps) on a single Xilinx UltraScale+ FPGA. Furthermore, a better utilization of FPGA resources is achieved compared to existing CRC implementation for HMC controller (up to 70 % savings).
Keywords
FPGA, CRC, high-speed processing, Ethernet, HMC
Authors
KEKELY, L.; CABAL, J.; KOŘENEK, J.
Released
28. 5. 2019
Publisher
Springer International Publishing
Location
Neuvedeno
ISBN
978-3-030-18655-5
Book
Architecture of Computing Systems - ARCS 2019
Pages from
211
Pages to
223
Pages count
13
URL
https://www.fit.vut.cz/research/publication/11987/
BibTex
@inproceedings{BUT157182, author="Lukáš {Kekely} and Jakub {Cabal} and Jan {Kořenek}", title="Effective FPGA Architecture for General CRC", booktitle="Architecture of Computing Systems - ARCS 2019", year="2019", pages="211--223", publisher="Springer International Publishing", address="Neuvedeno", doi="10.1007/978-3-030-18656-2\{_}16", isbn="978-3-030-18655-5", url="https://www.fit.vut.cz/research/publication/11987/" }