Impact of subcircuit selection on the efficiency of CGP-based optimization of gate-level circuits

conference paper

English

Various EA-based methods have been applied to design and optimize logic circuits since the early nineties. The unconventional methods, however, typically suffer from various scalability issues preventing them to be adopted in practice. Recent improvement in the fitness computation procedure connected with the introduction of formal methods in the fitness evaluation such as SAT solvers or BDDs enabled pushing of the limits forward and approaching the complexity of industrial problems. It was demonstrated that EAs can be applied to optimize gate-level circuits consisting of thousands of gates without introducing any decomposition technique. Despite that, the efficiency decreases with increasing the circuit complexity. This problem can be managed by adopting the concept of the so-called iterative resynthesis based on the extraction of smaller sub-circuits from a complex circuit, their local optimization followed by the implantation back to the original circuit. Recently, a method based on the computation of so-called cuts was proposed. In this paper, we propose an alternative approach which is able to select more complex sub-graphs consisting of more nodes and more inputs. Compared to the previous method, the proposed approach allows to improve the efficiency of the optimization. More than 9% and 20% reduction was observed on the highly optimized logic and arithmetic circuits, respectively.

Cartesian Genetic Programming, Logic Synthesis, CombinationalCircuits

KOCNOVÁ, J.; VAŠÍČEK, Z.

13. 7. 2019

Association for Computing Machinery

New York

978-1-4503-6748-6

GECCO '19 Proceedings of the Genetic and Evolutionary Computation Conference Companion

377

378

2

https://www.fit.vut.cz/research/publication/11921/