Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination

conference paper

English

A processor forms the basis of almost most of today's electronic devices. In embedded systems, the emphasis is put not only on high performance but also on the small size and low power consumption. Application-specific instruction set processors present a solution that may be optimized for specific applications by different modifications of their parameters where the trade-offs among the parameters may be represented by a Pareto frontier. In this paper, we propose a novel method of Pareto frontier merging to allow the optimization of a processor for a whole set of applications rather than a single one. We provide an experimental evaluation of the method on a model of a RISC-V processor and we show that the proposed method provides better approximation of the source Pareto frontiers than the state-of-the-art methods.

Pareto frontier, processor optimization, ASIP

PODIVÍNSKÝ, J.; ČEKAN, O.; KRČMA, M.; BURGET, R.; HRUŠKA, T.; KOTÁSEK, Z.

25. 2. 2020

IEEE Circuits and Systems Society

San José

978-1-7281-3427-7

2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS)

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https://www.fit.vut.cz/research/publication/12081/

LASCAS_2020_DSP1_5_CR_27_Podivinsky.pdf