Publication detail

Universal Pseudo-random Generation of Assembler Codes for Processors

ČEKAN, O. ZACHARIÁŠOVÁ, M. KOTÁSEK, Z.

Original Title

Universal Pseudo-random Generation of Assembler Codes for Processors

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

The paper describes a universal generation of test stimuli  based  on  solving  constraints.  The  architecture  of  the universal generator consists of two formal models. The first one is used for describing the generated scenario and the second one for  specifying  constraints  for  this  scenario.  The  generation  of the  assembler  programs  for  Application-Specific  Instruction-set Processors (ASIPs) is an example of the use of this architecture. The  necessary  steps  needed  to  generate  a  valid  assembler  code are  described.  The  quality  of  the  generator  is  measured by  the instruction and statement coverage in functional verification.

Keywords

universal generator, assembler, processor, functional verification

Authors

ČEKAN, O.; ZACHARIÁŠOVÁ, M.; KOTÁSEK, Z.

Released

1. 1. 2015

Publisher

COST, European Cooperation in Science and Technology

Location

Grenoble

Pages from

70

Pages to

73

Pages count

4

URL

http://www.median-project.eu/wp-content/uploads/18_IV-2_median2015.pdf

BibTex

@inproceedings{BUT168443,
  author="Ondřej {Čekan} and Marcela {Zachariášová} and Zdeněk {Kotásek}",
  title="Universal Pseudo-random Generation of Assembler Codes for Processors",
  booktitle="Proceedings of The Third Workshop on Manufacturable and Dependable Multicore Architectures at Nanoscale",
  year="2015",
  pages="70--73",
  publisher="COST, European Cooperation in Science and Technology",
  address="Grenoble",
  url="http://www.median-project.eu/wp-content/uploads/18_IV-2_median2015.pdf"
}