Publication detail

New Methods for Synthesis and Approximation of Logic Circuits

VAŠÍČEK, Z.

Original Title

New Methods for Synthesis and Approximation of Logic Circuits

Type

habilitation thesis

Language

English

Authors

VAŠÍČEK, Z.

Released

18. 10. 2016

Location

Brno

Pages count

194

URL

https://www.fit.vut.cz/research/publication/11742/

BibTex

@misc{BUT168627,
  author="Zdeněk {Vašíček}",
  title="New Methods for Synthesis and Approximation of Logic Circuits",
  year="2016",
  pages="194",
  address="Brno",
  url="https://www.fit.vut.cz/research/publication/11742/",
  note="habilitation thesis"
}