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KEKELY, M. HYNEK, K. ČEJKA, T.
Original Title
Pipelined ALU for effective external memory access in FPGA
Type
conference paper
Language
English
Original Abstract
The external memories in digital design are closely related to high response time. The most common approach to mitigate latency is adding a caching mechanism into the memory subsystem. This solution might be sufficient in CPU architecture, where we can reschedule operations when a cache miss occurs. However, the FPGA architectures are usually accelerators with simple functionality, where it is not possible to postpone work. The cache miss often leads to whole pipeline stall or even to data loss. The architecture we present in this paper reduces this problem by aggregating arithmetic operations into the memory subsystem itself. Fast data processing is achieved because arithmetic operations working with external data are offloaded. Our architecture reaches a speed of 200 Mp/s (operations carried out). It is designed to be used in systems with link speeds of 100 Gb/s. It outperforms other implementations by a factor of at least 3. The additional benefit of our architecture is reducing the number of memory transactions by a factor of two on real-world datasets.
Keywords
cache, external memory, FPGA, network monitoring
Authors
KEKELY, M.; HYNEK, K.; ČEJKA, T.
Released
26. 8. 2020
Publisher
Institute of Electrical and Electronics Engineers
Location
Kranj
ISBN
978-1-7281-9535-3
Book
2020 23RD EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2020)
Pages from
97
Pages to
100
Pages count
4
URL
https://ieeexplore.ieee.org/abstract/document/9217822
BibTex
@inproceedings{BUT169182, author="Michal {Kekely} and Karel {Hynek} and Tomáš {Čejka}", title="Pipelined ALU for effective external memory access in FPGA", booktitle="2020 23RD EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2020)", year="2020", pages="97--100", publisher="Institute of Electrical and Electronics Engineers", address="Kranj", doi="10.1109/DSD51259.2020.00026", isbn="978-1-7281-9535-3", url="https://ieeexplore.ieee.org/abstract/document/9217822" }