Publication detail

Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks

FUKAČ, T. MATOUŠEK, J. KOŘENEK, J. KEKELY, L.

Original Title

Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks

Type

conference paper

Language

English

Original Abstract

Increasing speed of network links continuously pushes up requirements on the performance of network security and monitoring systems, including their typical representative and its core function: an intrusion detection system (IDS) and pattern matching. To allow the operation of IDS applications like Snort and Suricata in networks supporting throughput of 100 Gbps or even more, a recently proposed pre-filtering architecture approximates exact pattern matching using hash-based matching of short strings that represent a given set of patterns. This architecture can scale supported throughput by adjusting the number of parallel hash functions and on-chip memory blocks utilized in the implementation of a hash table. Since each hash function can address every memory block, scaling throughput also increases the total capacity of the hash table. Nevertheless, the original architecture utilizes the available capacity of the hash table inefficiently. We therefore propose three optimization techniques that either reduce the amount of information stored in the hash table or increase its achievable occupancy. Moreover, we also design modifications of the architecture that enable resource-efficient utilization of all three optimization techniques together in synergy. Compared to the original pre-filtering architecture, combined use of the proposed optimizations in the 100 Gbps scenario increases the achievable capacity for short strings by three orders of magnitude. It also reduces the utilization of FPGA logic resources to only a third.

Keywords

hash functions, network security, pattern matching, high-speed networks

Authors

FUKAČ, T.; MATOUŠEK, J.; KOŘENEK, J.; KEKELY, L.

Released

6. 12. 2021

Publisher

Institute of Electrical and Electronics Engineers

Location

Auckland

ISBN

978-1-6654-2010-5

Book

2021 International Conference on Field-Programmable Technology, ICFPT 2021

Pages from

185

Pages to

193

Pages count

9

URL

BibTex

@inproceedings{BUT175767,
  author="Tomáš {Fukač} and Jiří {Matoušek} and Jan {Kořenek} and Lukáš {Kekely}",
  title="Increasing Memory Efficiency of Hash-Based Pattern Matching for High-Speed Networks",
  booktitle="2021 International Conference on Field-Programmable Technology, ICFPT 2021",
  year="2021",
  pages="185--193",
  publisher="Institute of Electrical and Electronics Engineers",
  address="Auckland",
  doi="10.1109/ICFPT52863.2021.9609859",
  isbn="978-1-6654-2010-5",
  url="https://ieeexplore.ieee.org/document/9609859"
}