Publication detail

A 650 kV/mu s Common-Mode Resilient CMOS Galvanically Isolated Communication System

JAVID, M. PTACEK, K. BURTON, R. KITCHEN, J.

Original Title

A 650 kV/mu s Common-Mode Resilient CMOS Galvanically Isolated Communication System

Type

journal article in Web of Science

Language

English

Original Abstract

This work presents a galvanically isolated chip-to-chip communication system that utilizes laterally coupled resonators in combination with a new differential full-wave receiver architecture. Lateral resonant coupling increases the isolation capability and significantly minimizes the intra-chip coupling capacitance of galvanic isolators beyond the limits of vertical coupling in standard CMOS. The presented system marries the merits of a laterally resonant coupled channel with a source-gate coupled low-power, low-latency RF detector architecture that enables high common-mode and differential noise immunity. A center-tapped transformer is used as the interface between the proposed fully differential receiver and the communication channel to further enhance the common-mode transient immunity (CMTI). The proposed system is integrated in a 0.25 mu m CMOS process with four metal layers and does not alter the native process or necessitate additional fabrication steps. The design does not require exotic packaging and achieves state-of-art CMTI of 650 kV/mu s at 5 kVpk isolation, sub-20ns propagation delay, and maintains a small form-factor of 0.95 mm(2). The GI system exhibits robust performance to fabrication variations, with less than +/- 0.3% and +/- 8% sensitivity to process variation and post-assembly chip distance offset, respectively.

Keywords

Couplings; Magnetic resonance; Capacitance; Magnetic domains; Transient analysis; Topology; Receivers; RF chip-to-chip communication; isolators; transceiver; lateral coupling; transformer; CMOS

Authors

JAVID, M.; PTACEK, K.; BURTON, R.; KITCHEN, J.;

Released

1. 2. 2022

Publisher

IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC

Location

PISCATAWAY

ISBN

1549-8328

Periodical

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

Year of study

69

Number

2

State

United States of America

Pages from

587

Pages to

598

Pages count

12

URL

https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9626774

BibTex

@article{BUT182455,
  author="JAVID, M. and PTACEK, K. and BURTON, R. and KITCHEN, J.",
  title="A 650 kV/mu s Common-Mode Resilient CMOS Galvanically Isolated Communication System",
  journal="IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS",
  year="2022",
  volume="69",
  number="2",
  pages="587--598",
  doi="10.1109/TCSI.2021.3124554",
  issn="1549-8328",
  url="https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9626774"
}