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KOŠAŘ, V. ŠIŠMIŠ, L. MATOUŠEK, J. KOŘENEK, J.
Original Title
Accelerating IDS Using TLS Pre-Filter in FPGA
Type
conference paper
Language
English
Original Abstract
Intrusion Detection Systems (IDSes) are a widely used network security tool. However, achieving sufficient throughput is challenging as network link speeds increase to 100 or 400 Gbps. Despite the large number of papers focusing on the hardware acceleration of IDSes, the approaches are mostly limited to the acceleration of pattern matching or do not support all types of IDS rules. Therefore, we propose hardware acceleration that significantly increases the throughput of IDSes without limiting the functionality or the types of rules supported. As the IDSes cannot match signatures in encrypted network traffic, we propose a hardware TLS pre-filter that removes encrypted TLS traffic from IDS processing and doubles the average processing speed. Implemented on an acceleration card with an Intel Agilex FPGA, the pre-filter supports 100 and 400 Gbps throughput. The hardware design is optimized to achieve a high frequency and to utilize only a few hardware resources.
Keywords
TLS, acceleration, FPGA, IDS, 100G Ethernet, 400G Ethernet
Authors
KOŠAŘ, V.; ŠIŠMIŠ, L.; MATOUŠEK, J.; KOŘENEK, J.
Released
9. 7. 2023
Publisher
IEEE Computer Society
Location
Tunis
ISBN
979-8-3503-0048-2
Book
Proceedings - IEEE Symposium on Computers and Communications
Pages from
436
Pages to
442
Pages count
7
URL
https://ieeexplore.ieee.org/document/10218049
BibTex
@inproceedings{BUT185159, author="Vlastimil {Košař} and Lukáš {Šišmiš} and Jiří {Matoušek} and Jan {Kořenek}", title="Accelerating IDS Using TLS Pre-Filter in FPGA", booktitle="Proceedings - IEEE Symposium on Computers and Communications", year="2023", pages="436--442", publisher="IEEE Computer Society", address="Tunis", doi="10.1109/ISCC58397.2023.10218049", isbn="979-8-3503-0048-2", url="https://ieeexplore.ieee.org/document/10218049" }