Modeling and design of novel architecture of multibit switched-capacitor sigma-delta converter with two-step quantization process

conference paper

English

This paper presents a novel architecture of high-order single-stage sigma-delta (ΣΔ) converter for sensor measurement. The two-step quantization technique was utilized to design of novel architecture of ΣΔ modulator. The time steps are interleaved to achieve resolution improvement without decreasing of conversion speed. This technique can be useful for low oversampling ratio. The novel architecture was designed to obtain high dynamic range of input signal, high signal-to-noise ratio and high reliability. This paper describes steps involved in a new VHDL design of a decimation filter for a ΣΔ modulator. Parameters of decimation filter are derived from the specifications of the overall ΣΔ modulator. The proposed architecture of switched-capacitor (SC) ΣΔ modulator was simulated with nonidealities blocks, such as sampling jitter, noise, and operational amplifier parameters (white noise, finite dc gain, finite bandwidth, slew rate and saturation voltages). The novel architecture of SC ΣΔ modulator with two-step quantization process was designed and simulated in MATLAB SIMULINK.

sigma-delta modulation, decimation filter, analog-to -digital conversion

Lukas Fujcik, Thibault Mougel, Jiri Haze, Radimir Vrba

2006

1. 1. 2006

Morne, Mauritius

0-7695-2540-7

The International Conference on Systems, IEEE Computer Society

130

135

6