Publication detail

Testing PCBs Based on Boundary Scan and EDIF Data Analysis

KOTÁSEK, Z. TOMÍŠEK, P. ZBOŘIL, F.

Original Title

Testing PCBs Based on Boundary Scan and EDIF Data Analysis

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

The paper describes a practical approach to testing PCBs with Xilinx FPGAs. The approach is based on a PCB netlist analysis which is an integral part of EDIF data (Electronic Design Interchange Format), revealing the existing connections on the PCB through the Boundary Scan chain and comparing the two results. It is also supposed that the developed software tools will be used for debugging PCBs with Xilinx FPGAs. The goal of the research activities is to develop an easy to use, efficient and user friendly software tools.

Keywords

Boundary Scan, PCBs Testing, Xilinx FPGAs, EDIF Data Analysis

Authors

KOTÁSEK, Z.; TOMÍŠEK, P.; ZBOŘIL, F.

Released

1. 1. 1998

Publisher

unknown

Location

Szczyrk

ISBN

83-908409-6-0

Book

Proceedings of the DDECS'98

Pages from

95

Pages to

101

Pages count

7

BibTex

@inproceedings{BUT191444,
  author="Zdeněk {Kotásek} and Petr {Tomíšek} and František {Zbořil}",
  title="Testing PCBs Based on Boundary Scan and EDIF Data Analysis",
  booktitle="Proceedings of the DDECS'98",
  year="1998",
  pages="95--101",
  publisher="unknown",
  address="Szczyrk",
  isbn="83-908409-6-0"
}