Publication detail

RT Level Testability Analysis to Reduce Test Application Time

KOTÁSEK, Z. ZBOŘIL, F.

Original Title

RT Level Testability Analysis to Reduce Test Application Time

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

The paper describes the research activities the goal of which is to develop a methodology that solves the problem of the RT level testability analysis in a complex way. On the basis of the RT level testability analysis the reduction in test application time can be achieved. A new model of RT level elements classification for the purposes of the RT level testability analysis is described. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in PROLOG environment are presented. The methodology for the RT level testability analysis and the principles of its implementation are described.

Keywords

RT Level Testability Analysis, Element Classification, PROLOG

Authors

KOTÁSEK, Z.; ZBOŘIL, F.

Released

1. 1. 1997

Publisher

unknown

Location

Budapest

ISBN

0-8186-8129-2

Book

Proceedings of the EUROMICRO 97

Pages from

104

Pages to

111

Pages count

8

BibTex

@inproceedings{BUT191445,
  author="Zdeněk {Kotásek} and František {Zbořil}",
  title="RT Level Testability Analysis to Reduce Test Application Time",
  booktitle="Proceedings of the EUROMICRO 97",
  year="1997",
  pages="104--111",
  publisher="unknown",
  address="Budapest",
  isbn="0-8186-8129-2"
}