Publication detail

A Choice of SM/DM Parallel ANN Implementation for Embedded Applications

DVOŘÁK, V. ČEJKA, R.

Original Title

A Choice of SM/DM Parallel ANN Implementation for Embedded Applications

Type

article in a collection out of WoS and Scopus

Language

English

Original Abstract

This paper examines implementations of a multi-layer perceptron (MLP) on bus-based shared memory (SM) and on distributed memory (DM) multiprocessor systems. The goal has been to optimize HW and SW architectures in order to obtain the fastest response possible. Prototyping parallel MLP algorithms for up to 8 processing nodes with the DM as well as SM memory was done using CSP-based TRANSIM tool. The results of prototyping MLPs of different sizes on various number of processing nodes demonstrate the feasible speedups, efficiency and time responses for the given CPU speed, link speed or bus bandwidth.

Keywords

Multi-layer perceptron, shared and distributed memory, modeling, communicating sequential processes

Authors

DVOŘÁK, V.; ČEJKA, R.

Released

1. 1. 2000

Publisher

IEEE Computer Society Press

Location

Edinburgh, Scotland

ISBN

0-7695-604-6

Book

Proceedings of the 7th IEEE International Conference on ECBS

Pages from

18

Pages to

23

Pages count

6

BibTex

@inproceedings{BUT192344,
  author="Václav {Dvořák} and Rudolf {Čejka}",
  title="A Choice of SM/DM Parallel ANN Implementation for Embedded Applications",
  booktitle="Proceedings of the 7th IEEE International Conference on ECBS",
  year="2000",
  pages="18--23",
  publisher="IEEE Computer Society Press",
  address="Edinburgh, Scotland",
  isbn="0-7695-604-6"
}