Publication detail
Návrh a implementace jednotky pro analýzu paketů
MIKUŠEK, P.
Original Title
Návrh a implementace jednotky pro analýzu paketů
English Title
Design and Implementation of Processing Unit for Packet Analysis
Type
article in a collection out of WoS and Scopus
Language
Czech
Original Abstract
Článek popisuje architekturu Header Field Extractor procesoru, který je určen pro analýzu paketů. Procesor je postaven na architektuře RISC a je řízen instrukční sadou navrženou pro rychlou analýzu paketů.
English abstract
This paper presents architecture of Header Field Extractor processor, which is dedicated for packet analysis. It extracts specific control information from packet's headers, which are important for further packet processing. Processor is based on RISC architecture and it is controlled by instruction set dedicated for packet analysis. As a target technology the Field Programmable Gate Array (FPGA) is supposed.
Keywords
RISC, FPGA, VHDL, COMBO6, analýza paketů
Key words in English
RISC, FPGA, VHDL, COMBO6, packet analysis
Authors
MIKUŠEK, P.
Released
28. 4. 2005
Publisher
Vysoké učení technické v Brně
Location
Brno
ISBN
80-214-2888-0
Book
Proceedings of the 11th Conference and Competition STUDENT EEICT 2005
Pages from
145
Pages to
148
Pages count
4
BibTex
@inproceedings{BUT192636,
author="Petr {Mikušek}",
title="Návrh a implementace jednotky pro analýzu paketů",
booktitle="Proceedings of the 11th Conference and Competition STUDENT EEICT 2005",
year="2005",
pages="145--148",
publisher="Vysoké učení technické v Brně",
address="Brno",
isbn="80-214-2888-0"
}