Publication detail

Decreasing Test Time by Scan Chain Reorganization

BARTOŠ, P. KOTÁSEK, Z. DOHNAL, J.

Original Title

Decreasing Test Time by Scan Chain Reorganization

Type

abstract

Language

English

Original Abstract

Abstract of the same name paper presented on DDECS Symposium 2011. In this paper, methodology for scan chain optimisation performed after physical layout is presented. It is shown how the methodology can be used to decrease test time of component under test if scan chain is reorganized. The principles of the methodology are based on eliminating some types of faults in the physical layout and subsequent reduction of the number of test vectors needed to test the scan chain. As a result, component test application time is decreased. The methodology was verified on several circuits, experimental results are provided and discussed. It is expected that the results of our methodology can be used in mass production of electronic components where any reduction of test time is of great importance.

Keywords

scan chain, test, time, reordering, reorganization, physical, layout

Authors

BARTOŠ, P.; KOTÁSEK, Z.; DOHNAL, J.

Released

14. 10. 2011

Publisher

Brno University of Technology

Location

Brno

ISBN

978-80-214-4305-1

Book

7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science

Pages from

108

Pages to

108

Pages count

1

BibTex

@misc{BUT192746,
  author="Pavel {Bartoš} and Zdeněk {Kotásek} and Jan {Dohnal}",
  title="Decreasing Test Time by Scan Chain Reorganization",
  booktitle="7th Doctoral Workshop on Mathematical and Engineering Methods in Computer Science",
  year="2011",
  pages="108--108",
  publisher="Brno University of Technology",
  address="Brno",
  isbn="978-80-214-4305-1",
  note="abstract"
}