Publication detail

Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation

KANDI, A. BAKSI, A. GAN, P. GUILLEY, S. GERLICH, T. BREIER, J. CHATTOPADHYAY, A. SHRIVASTWA, R. MARTINÁSEK, Z. BHASIN, S.

Original Title

Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation

Type

conference paper

Language

English

Original Abstract

In this work, we present various hardware implementations for the lightweight cipher ASCON, which was recently selected as the winner of the NIST organized Lightweight Cryptography (LWC) competition. We cover encryption + tag generation and decryption + tag verification for the ASCON hash function and ASCON AEAD. On top of the usual (unprotected) implementation, we present side-channel protection (threshold countermeasure) and triplication/majority-based fault protection. To the best of our knowledge, this is the first protected hardware implementation of ASCON with respect to side-channel and fault inject protection. The side-channel and fault protections work orthogonal to each other (i.e., either one can be turned on/off without affecting the other). We present ASIC and FPGA benchmarks for all our implementations (hash and AEAD) with/without countermeasures for varying input sizes.

Keywords

ASCON, Hardware Implementation, Side-Channel Attack, Threshold Implementation, Fault Attack, Countermeasure

Authors

KANDI, A.; BAKSI, A.; GAN, P.; GUILLEY, S.; GERLICH, T.; BREIER, J.; CHATTOPADHYAY, A.; SHRIVASTWA, R.; MARTINÁSEK, Z.; BHASIN, S.

Released

25. 9. 2024

Publisher

IEEE Computer Society

Location

Knoxville, Tennessee, USA

ISBN

979-8-3503-5412-6

Book

2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)

ISBN

2159-3477

Periodical

IEEE Computer Society Annual Symposium on VLSI proceedings

Year of study

July

Number

2024

State

United States of America

Pages from

307

Pages to

312

Pages count

6

URL

https://ieeexplore.ieee.org/document/10682712

BibTex

@inproceedings{BUT193538,
  author="Aneesh {Kandi} and Anubhab {Baksi} and Peizhou {Gan} and Sylvain {Guilley} and Tomáš {Gerlich} and Jakub {Breier} and Anupam {Chattopadhyay} and Ritu Ranjan {Shrivastwa} and Zdeněk {Martinásek} and Shivam {Bhasin}",
  title="Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation",
  booktitle="2024 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)",
  year="2024",
  journal="IEEE Computer Society Annual Symposium on VLSI proceedings",
  volume="July",
  number="2024",
  pages="307--312",
  publisher="IEEE Computer Society",
  address="Knoxville, Tennessee, USA",
  doi="10.1109/ISVLSI61997.2024.00063",
  isbn="979-8-3503-5412-6",
  issn="2159-3477",
  url="https://ieeexplore.ieee.org/document/10682712"
}