Publication detail

Reconfigurability of the Interconnect Architecture for Chip Multiprocessors

DVOŘÁK, V.

Original Title

Reconfigurability of the Interconnect Architecture for Chip Multiprocessors

Type

conference paper

Language

English

Original Abstract

As multiprocessors on a single chip are penetrating quickly new application areas in network and media processing, their optimum interconnect architecture is of interest. A fixed application-specific interconnect may provide sufficient performance in some cases, but nowadays one can also consider the use of run-time reconfigurable interconnect to speed-up specific communication patterns during execution of the algorithm. The paper promotes the idea that the performance improvement can result mainly from changing interconnect topology for local and global communication patterns. Some examples of reconfigurable interconnect, clarifying this concept, are presented and a required area overhead is discussed.

Keywords

Chip multiprocessors, reconfigurable interconnect, group communications

Authors

DVOŘÁK, V.

RIV year

2005

Released

28. 1. 2005

Publisher

Computer Science Press

Location

Dublin

ISBN

0-9544145-6-X

Book

Proceedigns of the 4th International Symposium on Information and Communication Technologies

Edition

ACM International Conference Proceedings Series

Pages from

136

Pages to

141

Pages count

6

BibTex

@inproceedings{BUT21438,
  author="Václav {Dvořák}",
  title="Reconfigurability of the Interconnect Architecture for Chip Multiprocessors",
  booktitle="Proceedigns of the 4th International Symposium on Information and Communication Technologies",
  year="2005",
  series="ACM International Conference Proceedings Series",
  pages="136--141",
  publisher="Computer Science Press",
  address="Dublin",
  isbn="0-9544145-6-X"
}