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STRNADEL, J.
Original Title
VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements
Type
conference paper
Language
English
Original Abstract
The work deals with testability analysis of data-path within register-transfer level digital circuits and with utilizing its results in selected areas in digital circuit diagnostics area. In the work, it is shown that it is advantageous if each module stored in a design library is equipped both with design-related information and special diagnostics-related information usable for testability-analysis purposes in our case. During our research, such information was described by means of a formal mathematical model based on so-called transparency conception. Proposed digraph-search based testability analysis method is described by means of instruments specified in the model.
Keywords
Testability analysis, data-path, register-transfer level, transparency, I-path concept, virtual port, digraph, test-pattern data-flow digraph, test-response data-flow digraph, graph algorithm, design for testability, scan, benchmark circuit.
Authors
RIV year
2005
Released
19. 4. 2005
Publisher
University of West Hungary
Location
Sopron
ISBN
963-9364-48-7
Book
Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop
Pages from
190
Pages to
193
Pages count
4
BibTex
@inproceedings{BUT21464, author="Josef {Strnadel}", title="VIRTA: Virtual Port Based Register-Transfer Level Testability Analysis and Improvements", booktitle="Proceedings of 8th IEEE Design and Diagnostic of Electronic Circuits and Systems Workshop", year="2005", pages="190--193", publisher="University of West Hungary", address="Sopron", isbn="963-9364-48-7" }